1. Field of the Invention
The present invention relates to standard cell placement and in particular to such placement for double patterning technology.
2. Related Art
To fabricate an integrated circuit (IC), a designer can use an electronic design automation (EDA) tool to create a schematic design. This schematic design can include circuits that are coupled together to perform one or more functions. The schematic design is translated into a representation of an actual physical arrangement of materials, which upon completion is called a design layout. Typically, materials are arranged in multiple layers for an IC. Therefore, the design layout includes several design layers.
After the design layers are complete, a fabrication process is used to actually form the appropriate materials on each layer. This process includes a photolithographic process that directs a light source at a mask. In general, the mask has opaque and transparent regions that when illuminated causes light to fall on photosensitive material in a desired pattern. For example, after light is shined through the mask onto a photosensitive material (e.g. positive resist), the light-sensitive material is subjected to a developing process to remove those portions exposed to light (or, alternatively, remove those portions not exposed to light when using a negative resist). Etching, deposition, diffusion, or some other material altering process is then performed on the patterned layer until a particular material is formed with the desired pattern in that layer. The result of the process is a predetermined arrangement of material in each layer.
In one design technique, a designer can use a library of standard cells to form the circuits, which in turn can be coupled to provide the desired functionality. Each standard cell is a defined group of transistor and interconnect structures that provides a Boolean logic function (e.g. AND, OR, XOR, inversion, etc.) or a storage function (e.g. a flip-flop or a latch). Each standard cell also has a layout view, which provides an effective manufacturing blueprint for a material layer.
With increasing demand for greater functionality in smaller ICs as well as for more complex systems (including, for example, mixed signal and systems on chip), IC object geometries are being driven to ever smaller dimensions. Notably, the ability to project an accurate image of very small objects onto an IC substrate is limited in part by the wavelength of light used during photolithography. For example, current lithographic processes can use wavelengths of 193 nm, which can achieve minimum object sizes and spacing of approximately 70 nm. The minimum object spacing λ on a mask is related to many factors, including the wavelength of light used. In general, a smaller wavelength leads to a smaller value of λ.
Unfortunately, the resolution limit of yet smaller object sizes is becoming difficult due to highly non-linear imaging behavior, which can magnify mask errors in non-intuitive ways. To improve resolution, a smaller wavelength of light (e.g. in the extreme ultraviolet (EUV) range) can theoretically be used, although it is quite difficult to use in actual IC fabrication. Therefore, designers have instead tried to use non-lithographic solutions to increase pattern density.
One such non-lithographic solution is called double patterning. In this technique, two masks can be used to expose the same IC substrate, thereby effectively doubling the object density in that layer. For example, FIG. 1A illustrates an exemplary target pattern 100, which because of the close spacing between objects would be impossible to print using a single mask. FIGS. 1B and 1C illustrate masks 101 and 102, respectively, which when exposed separately and subsequently combined can achieve the target pattern 100. Note that the cross hatching of the objects refers only to mask designation.
This technique can be extended to multiple patterning of N masks where N is an integer. The printable object spacing is reduced approximately by a factor of N because object spacing belonging to different masks is no longer limited by the wavelength of light. Regardless of design technique, given a set of objects to be printed, each object needs to be assigned to one and only one mask for photolithography. This procedure is called “coloring” or “color assignment” of objects where each color corresponds to a mask. The color assignment should be done such that objects in each mask of a particular color do not violate the minimum spacing limited by λ., which is related to the light wavelength. Note that with certain configurations in object layout, it is impossible to assign color to all objects such that all masks obey minimum spacing. This condition is called “un-colorable”, “illegal (infeasible) color assignment”, or “color conflict” by those skilled in the art. For example, FIG. 1F illustrates three objects 121, 122, and 123 with spacing μ (minimum spacing of different colored objects), which is less than λ (minimum spacing of same colored objects) that cannot be legally assigned two colors with minimum spacing (i.e. not exceeding λ) on the same mask.
In a standard cell library design, the layout of all objects belonging to a single cell must be colorable when considering only the objects from that cell. The same must also hold true independently for all standard cells in the library. However, when two standard cells are placed side-by-side, illegal color assignment can occur. The set of un-colorable objects includes at least one object from each of the two standard cells.
Assuming that objects belonging to a standard cell are confined within its boundaries, i.e. edges, if two cells are spaced far enough apart, then the minimum spacing of objects originating from two different cells will meet the minimum distance requirement of a colored mask. Therefore, when a coloring conflict of two standard cells is detected, spacing must be inserted between the two standard cells to produce a colorable layout involving objects from the two standard cells. In a standard cell design, all standard cells need to be spaced such that all their respective objects are colorable given the placement of the standard cells.
The present invention, which is described in detail below, can provide an improved technique to generate a colorable placement of standard cells in an IC design.